1. Field of the Invention
The present invention relates to a liquid crystal panel drive circuit and a liquid crystal display apparatus.
2. Description of the Related Art
In a liquid crystal display panel, pixels including transistors are arranged in rows and columns, with gate bus lines extending in the horizontal direction being connected to the gates of the pixel transistors, and data bus lines extending in the vertical direction being connected to the pixel capacitors. When data is to be displayed on the liquid crystal display panel, gate drivers drive the gate bus lines one after another to make transistors conductive on a successive line, and the data drivers write the data of one horizontal line to the pixels through the turned-on transistors.
When the gates are driven, the farther away from the gate drivers, the more distorted the gate signal will be because of the resistance and capacitance of the gate bus lines. The signal distortion brings about timing differences between the positions nearer to the gate drivers and the positions farther away from the gate drivers. In detail, the timing at which the gates open is increasingly delayed at the positions further away from the gate drivers compared with the positions nearer to the gate drivers. The timing at which the data drivers output signals for driving the liquid crystal thus needs to be determined by taking into account the gate signal distortion.
Where the timing at which the gates open is delayed at positions far away from the gate drivers due to the gate signal distortion, the data supposed to be written at this pixel position may fail to be written, and the data of next timing (i.e., the data of the next line) may be written at this pixel position. In order to avoid this, the data write timing of the data drivers needs to be controlled such as to match the gate timing at the positions far away from the gate drivers. Such setting, however, ends up reducing the data write timing at the positions nearer to the gate drivers.
As liquid crystal display panels are manufactured with an increasingly fine resolution, the horizontal cycle shortens, resulting in the difficulties in securing a sufficient data write time. Also, as the liquid crystal display panels are manufactured with an increasingly large panel size, the gate bus lines are elongated, thereby making the effect of gate signal distortion increasingly conspicuous. The finer and larger the liquid crystal display panels, therefore, the more difficult it is to secure a sufficient data write time.
Accordingly, there is a need for a liquid crystal display apparatus and drive circuit that can secure a sufficient data write time.
The timing at which the data drivers write data needs to be accurately controlled. This is especially so when the liquid crystal display panels become increasingly finer and larger. Conventionally, the data write time is determined by applying the data tested for a particular liquid crystal display panel to other types of liquid crystal display panels, or is determined by applying the empirical knowledge accumulated over the years to various types of liquid crystal display panels. This may result in a certain type of a liquid crystal display panel suffering a write failure.
Accordingly, there is a need for a liquid crystal display apparatus that can determine the data write time reliably and accurately regardless of the types of liquid crystal display panels and the delay characteristics of gate bus lines.
In order to enlarge the display size under the limitation of a given physical size of a liquid crystal display apparatus, the frame portion surrounding the display portion needs to be reduced in size. In order to achieve this, it is preferable to provide signal lines coupled to the drivers within the liquid crystal display panel (i.e., on the TFT board) rather than on the circuit boards that are conventionally provided in the frame portion. In such a configuration, the drivers are connected in a cascade connection.
Accordingly, there is a need for a configuration having signal lines provided inside the liquid crystal display panel and drivers connected in a cascade connection wherein the data drivers operate at the timing that is properly controlled regardless of differences in the signal propagation lengths and the presence of signal distortion.